1. Field of the Invention
This disclosure relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device including a process of forming a self-aligned contact pad.
2. Description of the Related Art
Due to the reduction in the design rule of semiconductors, a Self-Aligned Contact (SAC) pad forming process has been added in the contact pad forming process. The SAC pad forming process uses a high etch selectivity between materials, thus securing a sufficient process margin in the exposure process and the etch process in spite of the reduction of the design rule. For instance, when forming an SAC hole in a first interlayer insulating layer of a semiconductor DRAM device, a hard mask is formed on a gate conductive film and a spacer is formed on the sidewall of the gate conductive film. In this case, the hard mask and the spacer are formed of a silicon nitride having a high etch selectivity with respect to the first interlayer insulating layer composed of silicon oxide.
FIG. 1 is a cross-sectional diagram illustrating an etch path in a self-aligned etch process (hereinafter refererred to as a “SAC hole etch process”) according to the related art. As shown by the arrows in FIG. 1, the etching of the first interlayer insulating layer 120 advances in a vertical direction, while the etching of the hard mask 116 of the gate electrode structure 110 advances with a predetermined inclination. As a result, the spacer 118 of the gate electrode structure 110, i.e., the shoulder of the gate electrode structure 110 becomes the weakest region after the etching process. In this specification, the term “shoulder of conductive line structure” or “shoulder” corresponds to a part of the spacer measured before or after the SAC hole etch process, and represents the upper edge of the conductive line structure. Hence, in order to use the self-aligned etch process, the thickness of the shoulder of the gate electrode structure 110, should have at least a predetermined thickness. Since the thickness of the shoulder of the gate electrode structure 110 depends on the thickness of the hard mask 116 and the thickness of the spacer 118, the thickness of the hard mask 116 and the thickness of the spacer 118 should be greater than predetermined values. Moreover, as the thickness of the hard mask 116 increases, an overall height of the gate electrode structure 110 also increases. More specifically, with the increase of the semiconductor device integration, since the critical dimension (CD) of the gate electrode structure 110 is decreased, the aspect ratio of the gate electrode structure 110 is increased.
The increase in the aspect ratio of the gate electrode structure makes it difficult to completely fill the interlayer insulating material between the gate electrode structures. If the gap filling characteristic of the interlayer insulating layer is poor, voids or similar imperfections are generated in the interlayer insulating layer.
FIG. 2 is a Scanning Electron Microscope (SEM) photograph showing voids generated in the first interlayer insulating layer between the gate electrode structures. To prevent voids, it is necessary to reduce the height of the gate electrode structure, which is limited.
One method of reducing the height of the gate electrode structure is to reduce the height of the gate conductive film. However, this method cannot be a realistic alternative because it reduces the surface area of the gate conductive film resulting in an increase of the resistance of the gate line.
Another method is to reduce the thickness of the hard mask and the thickness of the spacer. However, this method also has a limitation related to the SAC pad forming process. As aforementioned, to ensure the shoulder of the gate electrode structure has a sufficient thickness after the self-aligned etch process, the thickness of the hard mask and the thickness of the spacer should be thick, and therefore, there is a limitation in reducing the thickness of the hard mask and the thickness of the spacer.
When the design rule is 0.11 μm, etch gases used in the self-aligned etch process can be a combination of C5F8/O2/Ar or a combination of C4F6/O2/Ar. If the thickness of the first interlayer insulating layer is greater than 4000 Å, the shoulder thickness of the gate electrode structure should be at least 3500 Å. Then, if the thickness of the hard mask and the thickness of the spacer are increased so as to secure a sufficient shoulder thickness, the space between the gate electrode structures becomes narrow, so that the gap filling characteristics of the first interlayer insulating layer are deteriorated. Accordingly, there is a limitation to increasing the thickness of the shoulder.
FIG. 3 is a graph of the shoulder thickness with respect to the thickness of the hard mask. Referring to FIG. 3, if the thickness of the hard mask is decreased by 100 Å, the thickness of the shoulder is decreased by about 30 Å. Thus, to ensure that the shoulder thickness is above 350 Å, the thickness of the hard mask should be above 1800 Å, and should be above 2000 Å for application to mass production. When using the conventional SAC pad forming process, it is not easy to decrease the thickness of the hard mask below 2000 Å, so there is a limitation in reducing the aspect ratio of the gate electrode structure.
As the overall height of the gate electrode structure increases, another problem, i.e., deterioration of the critical dimension (CD) uniformity of the gate electrode structure may occur.
FIG. 4 is a graph of a deviation between a design CD and a measured CD after line and space patterns are formed with respect to the designed CD. Referring to FIG. 4, measurements were made when the overall height of the gate electrode structure was 1800 Å, 2200 Å, and 2600 Å. When the design CD is constant and the overall height of the gate electrode structure is increased, it is seen that the deviation between the design CD and the measurement CD is increased. The increase in the deviation between the CDs means that the uniformity of the CD becomes worse with respect to the position of the line as well as on the same line.
If the uniformity of the CD becomes worse, the linearity of the gate electrode structure becomes worse, and it is difficult to obtain a gate electrode structure having a desired shape. If the measurement CD is smaller than the design CD, the refresh characteristics of the DRAM device may be deteriorated. If the measurement CD is larger than the design CD, tRCD failure may occur. Thus, if the CD uniformity is bad, the performance of the transistor may be deteriorated, thereby lowering the reliability of the semiconductor device.
As the design rule decreases and the height of the gate electrode structure increases, another problem, for example, a middle bridge, may occur. In the middle bridge phenomenon, adjacent SAC pads are short-circuited in a length direction of the gate electrode structure when forming the SAC pad. This middle bridge phenomenon occurs because the height of the first interlayer insulating layer to be removed increases but the interval between the SAC pads, specifically the interval between the SAC pads in the length direction of the gate electrode structures, is reduced. Because of a narrow interval between the SAC pads, if the first interlayer insulating layer is overetched in the self-aligned etch process or in a post-etch cleaning process, the SAC holes may connect each other.
A method of forming a SAC pad that attempts to solve this problem is disclosed in U.S. Pat. No. 6,265,296 by Yen et al (“Yen”). In this method, a SAC contact pad is formed using a silicon nitride formed on a blanket insulating layer as a hard mask. That is, a silicon nitride film pattern having an opening partly exposing a source/drain region and a gate electrode structure is formed on the blanket insulating layer, and then a self-aligned etch process of the blanket insulating layer is performed through the opening. Since the silicon nitride film pattern is used as the etch mask instead of a photoresist pattern, the generation of an organic by-product due to a reaction between the photoresist and the etch gas can be prevented or suppressed. As a result, a cleaning process to remove the organic by-product can be omitted or the organic by-product can be completely removed in the cleaning process. However, as described later, if the photoresist pattern is not used as the etch mask, it is difficult to secure a process margin of the SAC hole etch process.
Embodiments of the invention address these and other disadvantages of the conventional art.